A recent trend in semiconductor memories is to fabricate three dimensional (3D) integrated circuits (3D IC). 3D ICs include a variety of structures, such as die on silicon interposer, stacked dies, multi-tiered, stacked CMOS structures, or the like. These 3D circuits offer a host of advantages over traditional two dimensional circuits: lower power consumption, higher memory cell density, greater efficiency, alleviating bottlenecks, shorter critical path delays, and lower area cost to name just a few. Stacked die 3D IC are constructed by vertically stacking two dimensional chips and providing power and signal communication connections between the chips (for example, using through-substrate vias, TSV). Alternatively, 3D IC can be constructed using a single die with integrated components arranged in three dimensions into a plurality of tiers. Each tier can have its own active device layer and/or interconnect structure. Each pair of adjacent tiers are separated from each other by an insulating layer or thin semiconductor substrate or layer. Unfortunately, the performance of these 3D IC is limited by the performance variation of the worst-performing chip or tier in the vertical stack.